1. Field of the Invention
The present invention relates to a method for producing a bipolar transistor having a laterally graded emitter, and more particularly to a method for producing a bipolar transistor which prevents a degradation phenomenon of the transistor resulting from a reduction in the lateral electric field intensity. This is achieved by grading an emitter junction by way of refilling polycrystalline silicon along an emitter window.
2. Description of the prior art
In general, a hot carrier phenomenon occurring in response to a reverse bias in an emitter junction heightens a degradation of a bipolar transistor fabricated using a conventional method for producing a BiCMOS, or a submicron grade (under 1 .mu.m), bipolar transistor.
To improve the degradation of a transistor resulting from a hot carrier phenomenon, a Mitsubishi LSI R&D center in Japan introduced, at IEMD in 1990, a method for fabricating a semiconductor device with improved degradation by reducing lateral electric field intensity by laterally grading the shape of the transistor emitter junction.
FIG. 1 is a vertical sectional view explaining a conventional bipolar transistor.
As shown in FIG. 1, a conventional method of producing a transistor comprises a step of growing an n.sup.+ buried layer (not shown) and an n.sup.- epitaxial layer 1 over p type substrate (not shown), growing oxide layer 3a over epitaxial layer 1, forming p type base region 2 in epitaxial layer 1, growing oxide layer 3b over oxide layer 3a, forming emitter window 4 by etching a predetermined region of oxide layer 3, forming n.sup.- type emitter region 5a, forming oxide side wall 6, and forming n.sup.+ type emitter region 5b.
The above mentioned production method is as follows:
The n.sup.- buried layer and n.sup.+ type epitaxial layer 1 are grown over the p type substrate and then oxide layer 3a is formed using an annealing process. Subsequently, ions are implanted into a predetermined region of epitaxial layer 1 using a conventional method for fabricating a bipolar transistor.
As a result, p type base region 2 is formed consisting of p.sup.- type region 2a and p+ type region 2b.
Oxide layer 3b is formed over oxide layer 3a using a chemical vapor deposition (CVD) process.
Accordingly, a layer of oxide 3 is formed comprising oxide layers 3a and 3b.
A predetermined region of oxide layer 3 is etched such that an emitter window is formed.
N.sup.- type ions are implanted and diffused in base region 2 through emitter window 4 such that n- type emitter region 5a is formed. After the deposition of oxide layer 3, a dry etching process is performed. Oxide sidewall 6 is thus formed in emitter window 4.
N.sup.+ type ions are implanted and diffused in n.sup.- type emitter region 5a through emitter window 4 and restricted by previously formed oxide sidewall 6 such that n+ type emitter region 5b is formed therein as shown in FIG. 1.
Emitter region 5 is shown consisting of n.sup.- type emitter region 5a and n.sup.+ type emitter region 5b.
Subsequently, oxide layer 3 formed over p type base region 2 is etched such that a base window results.
After performance of the above-mentioned steps, a well known gate formation process is performed.
Hence, in a conventional production method, after n.sup.- type ions are implanted and oxide sidewall 6 is formed over n.sup.- type ion implanted region 5a, n.sup.+ type ions are implanted.
As a result, because ion implanted regions are activated during the annealing process, the conventional method for fabricating a bipolar transistor is disadvantageous since it results in the formation of a deep junction.
Furthermore, silicon overetch existing due to the formation of oxide sidewall 6 acts as a trap creating a peak field under oxide layer 3 deteriorating a current handling capability to the oxide sidewall 6 and so on. Hence, such a prior art method bipolar transistor fabrication can not be relied upon in production of a submicron grade of emitter of polycrystalline silicon.
FIG. 2 is a vertical sectional view showing a second method for forming a conventional bipolar transistor.
FIG. 2 shows a bipolar transistor having a laterally graded emitter which includes polycrystalline silicon sidewall 7 for improving a hot carrier phenomenon. The method for forming such bipolar transistor includes a first step of growing a second conductivity type buried layer (not shown) and epitaxial layer 1 over a first conductivity type substrate (not shown), a second step of growing oxide layer 3a over epitaxial layer 1, a third step of forming a first conductivity type base region 2 over a predetermined region of epitaxial layer 1, a fourth step of forming oxide layer 3 by growing an oxide layer 3b over oxide layer 3a, a fifth step of forming an emitter window over a predetermined region of first conductivity type base region 2 by etching oxide layer 3, a sixth step of forming a second conductivity type n.sup.- low concentration polycrystalline silicon sidewall 7 using a polycrystalline silicon deposition process and implanting to form sidewall 7 along emitter window 4, a seventh step of forming a second conductivity type n.sup.+ high concentration polycrystalline silicon region by a polycrystalline silicon deposition process and implanting, and an eighth step of diffusing emitter region 5 using an ion diffusion process.
The above-mentioned second conventional production method is summarized as follows.
The buried layer and n.sup.+ type epitaxial layer 1 are grown over p type substrate and then oxide layer 3 is formed over epitaxial layer 1 using an annealing process.
Ions are implanted and diffused in a predetermined region of epitaxial layer 1 using well-known bipolar transistor fabrication techniques.
As a result, p type base region 2 comprising p- type region 2a and p.sup.+ type region 2b is formed.
Oxide layer 3b is grown over oxide layer 3a using a chemical vapor deposition (CVD) process to form oxide layer 3.
The predetermined region of oxide layer 3 is etched such that emitter window 4 is formed over p.sup.- type base region.
After formation of n.sup.- type polycrystalline silicon layer, a dry etching is performed such that n.sup.- type polycrystalline silicon sidewall 7 is formed in emitter window 4.
N.sup.+ type polycrystalline silicon 8 is also formed in emitter window 4 limited only by the formation of n.sup.- type polycrystalline silicon sidewall 7. Finally, n.sup.+ type polycrystalline silicon is formed using a photolithographic etching technique which contacts with p.sup.- type base region 2a.
While a rapid thermal annealing (RTA) or a normal annealing process is performed, n.sup.+ type polycrystalline silicon 8 and sidewall 7 are employed as the diffusion source. N.sup.+ type emitter region 5b and the n.sup.- type emitter regions 5a are formed in p.sup.- type base region by self-aligning n+ type emitter region 5b with n.sup.+ type polycrystalline silicon 8 and n.sup.- type emitter regions 5a with sidewalls 7.
At this time, polycrystalline silicon sidewalls 7 are doped by the regions of n+ type polycrystalline silicon 8 making contact therewith.
The above conventional bipolar transistor fabrication techniques are disadvantageous. The single crystal silicon layer and the polycrystalline silicon layer cannot be selectively etched by means of a reactive ion etching (RIE) process during formation of n.sup.- type polycrystalline silicon sidewall 7 such that etching can be easily stopped. Further, such an emitter diffused transistor construction having a laterally graded emitter structure cannot be easily formed given existing dopant diffusivity characteristics.